1. Field of the Invention
The present invention relates to a method and a stencil mask for exposing patterns of semiconductor devices, more specifically, it relates to a pattern exposing method in which a design pattern of a device is divided into a plurality of unit patterns, which are then transferred onto a semiconductor substrate in an adjoining arrangement to be connected and complete an integral device pattern.
2. Description of the Related Art
Recent ultra-fine patterns such as in a 16 M DRAM (dynamic random access memory) have a fine line width and a fine line interval. The line width or interval (frequently referred to as "design rule") decreases as the memory capacity increases, for example, from 1 .mu.m for 1 M DRAM to 0.7 .mu.m for 4 M, 0.5 .mu.m for 16 M, 0.2 .mu.m for 64 M, and so on.
Since most of such an ultra-fine device pattern is generally composed of a plurality of repeat patterns, a stencil transfer exposure method is proposed, in which the portion of repeat patterns is divided into a plurality of corresponding unit patterns, transmitting openings having a shape defining a charged particle beam conforming to the respective unit patterns are disposed in a stencil mask, which is then placed in an optical arrangement, a transmitting opening is selected in accordance with the unit patterns to be exposed, the charged particle beam is irradiated through the selected opening to expose the selected unit pattern at the predetermined sites on a substrate, and irradiation or exposure of other unit patterns is repeated for other predetermined sites on the substrate in an adjoining relationship with each other to be connected with each other on the substrate and thereby complete the pattern of the portion of repeat patterns, the other portion of non-repeat patterns being exposed by using a variable rectangular beam.
In the stencil transfer exposure method, when unit patterns are exposed in an adjoining arrangement, a location error or displacement occurs at the connecting region of two adjoining unit patterns to significant extent due to the limited accuracy of positioning. Such a location error causes a problem in recent ultra-fine device patterns. For example, a transversal displacement between adjoining unit patterns as shown in FIG. 5 causes an excessively small width of pattern lines 51 and 52 at the connecting region as shown in FIG. 5, which will result in a connection failure, disconnection, or other defects. It is therefore necessary to take measures to prevent location errors while exposing unit patterns in an adjoining arrangement.
A method is proposed in Japanese Unexamined Patent Publication (Kokai) No. 62-206829, in which exposure is carried out such that the ends of pattern lines of two adjoining unit patterns are partially overlapped as shown in FIG. 4(a) of the publication.
This method, however, inevitably leads to an excessive broadening of the exposed pattern lines at the connecting region, since the connecting ends are exposed twice. This will cause a problem, particularly for recent ultra-fine patterns, in that an undesired connection could occur between two adjacent lines which must not be connected.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method and a stencil mask for exposing a semiconductor device pattern which ensures a reliable connection between the pattern lines of adjoining unit patterns while avoiding an excessive broadening of the exposed pattern lines at the connection region.
There is provided, according to the present invention, a method of exposing a semiconductor device pattern onto a semiconductor substrate by repeatedly exposing in an adjoining arrangement a plurality of unit patterns obtained by dividing at least part of a device pattern and connecting the unit patterns to complete said part of the device pattern on the substrate, which comprises:
dividing at least part of a device pattern into a plurality of unit patterns;
preparing a stencil mask provided with transmitting openings having shapes conforming to the respective unit patterns, pattern lines to be connected with each other bridging the adjoining unit patterns having at least one connecting end provided with at least one protrusion having a width less than that of the corresponding pattern lines;
placing the stencil mask in an optical arrangement for projecting the unit patterns onto the substrate;
irradiating a beam of charged particles or light through one of the openings for exposing one corresponding unit pattern onto the predetermined sites of the substrate; and
repeating said irradiation through other openings for exposing the respective corresponding unit patterns onto the respective predetermined sites of the substrate until said part of the device pattern is completely transferred onto the substrate.
There is also provided, according to the present invention, a stencil mask used for exposing patterns of semiconductor devices onto a semiconductor substrate by repeatedly exposing in an adjoining arrangement a plurality of unit patterns obtained by dividing at least part of a device pattern, thereby connecting the unit patterns to complete said part of the device pattern on the substrate, which comprises:
a plate body having a plurality of openings disposed therein for transmitting a beam of charged particles or light therethrough, said openings having shapes conforming to the respective unit patterns, pattern lines to be connected bridging the adjoining unit patterns having at least one connecting end provided with at least one protrusion having a width less than that of the corresponding pattern lines.
To more easily effect a connection between pattern line ends under a given positioning accuracy, preferably one of a pair of pattern lines to be connected has a smooth connecting end and the other has a connecting end provided with at least one protrusion.
From the view point of manufacturing an ultra-fine pattern such that pattern lines have a width or a interval less than 1 .mu.m, one protrusion should be provided on at least one of the pair of connecting ends.
In the present invention, the pattern line ends are partially exposed twice upon exposing the adjoining unit patterns. The protrusion provided at at least one of the connecting ends decreases the amount of irradiation beam energy introduced in the duplicately exposed region, in comparison with that introduced when both connecting ends are smooth. This enables an excessive broadening of the exposed lines at the connecting region to be avoided while ensuring a reliable connection between lines.